Through the continuous development of the technology of integrated circuits, one system-on-chip (SOC) has more and more components and functions. However, the power consumption of SOC also increases. Therefore, how to reduce the power consumption of the SOC has become the trend of follow-up research. Generally speaking, electronic devices (e.g. wearable electronic devices, communication devices, etc.) are expected to operate for a long period of time and have a thinner and lighter design. Therefore, the battery capacity of these electronic devices is limited.
For such reasons, an SOC is usually designed to have two modes. One of the modes is the active mode that allows the SOC to operate normally. In the active mode, power is supplied to respective components in the SOC normally, so as to fully perform functions of the SOC. The other mode is a normally-off mode used when the SOC is not in use for a long period of time. In the normally-off mode, data in all computing components in the SOC are firstly stored to a non-volatile memory, and then power supply to the computing components is turned off to significantly reduce power consumption of the SOC. When the SOC returns from the normally-off mode to the active mode, the data is read from the non-volatile memory to each of the computing component. Then, the data are validated to prevent errors when retrieving the data from the non-volatile memory. However, since the SOC in the normally-off mode still needs to transmit the data from the computing components to the non-volatile memory or read from the non-volatile memory, and such operation requires some execution time, power still need to be supplied to other computing components and relevant circuits, resulting in additional power consumption. Therefore, the normally-off mode is only suitable when an electronic device is idling for a long period of time. For example, the operation cycle of the normally-off mode need to be longer than the break-even time (BET).